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11.10   Modeling Delay

Verilog has a set of built-in methods to define delays. This is very important in ASIC physical design. Before we start layout, we can use ASIC cell library models written in Verilog that include logic delays as a function of fanout and estimated wiring loads. After we have completed layout, we can extract the wiring capacitance, allowing us to calculate the exact delay values. Using the techniques described in this section, we can then back-annotate our Verilog netlist with postlayout delays and complete a postlayout simulation.

We can complete this back-annotation process in a standard fashion since delay specification is part of the Verilog language. This makes working with an ASIC cell library and the ASIC foundry that will fabricate our ASIC much easier. Typically an ASIC library company might sell us a cell library complete with Verilog models that include all the minimum, typical, and maximum delays as well as the different values for rising and falling transitions. The ASIC foundry will provide us with a delay calculator that calculates the net delays (this is usually proprietary technology) from the layout. These delays are held in a separate file (the Standard Delay Format, SDF, is widely used) and then mapped to parameters in the Verilog models. If we complete back-annotation and a postlayout simulation using an approved cell library, the ASIC foundry will "sign off" on our design. This is basically a guarantee that our chip will work according to the simulation. This ability to design sign-off quality ASIC cell libraries is very important in the ASIC design process.

11.10.1   Net and Gate Delay

We saw how to specify a delay control for any statement in Section 11.6. In fact, Verilog allows us to specify minimum, typical, and maximum values for the delay as follows [Verilog LRM7.15]:

#(1.1:1.3:1.7) assign delay_a = a; // min:typ:max

We can also specify the delay properties of a wire in a similar fashion:

wire #(1.1:1.3:1.7) a_delay; // min:typ:max

We can specify delay in a wire declaration together with a continuous assignment as in the following example:

wire #(1.1:1.3:1.7) a_delay = a; // min:typ:max

but in this case the delay is associated with the driver and not with the wire .

In Section 11.9.1 we explained that we can specify a delay for a logic primitive. We can also specify minimum, typical, and maximum delays as well as separate delays for rising and falling transitions for primitives as follows [Verilog LRM4.3]:

nand #3.0 nd01(c, a, b);
nand #(2.6:3.0:3.4) nd02(d, a, b); // min:typ:max
nand #(2.8:3.2:3.4, 2.6:2.8:2.9) nd03(e, a, b);
// #(rising, falling) delay

The first NAND gate, nd01 , has a delay of 3 ns (assuming we specified nanoseconds as the timescale) for both rising and falling delays. The NAND gate nd02 has a triplet for the delay; this corresponds to a minimum (2.6 ns), typical (3.0 ns), and a maximum delay (3.4 ns). The NAND gate nd03 has two triplets for the delay: The first triplet specifies the min/typ/max rising delay ( '0' or 'x' or 'z' to '1' ), and the second triplet specifies the min/typ/max falling delay ( '1' or 'x' or 'z' to '0' ).

Some primitives can produce a high-impedance output, 'z' . In this case we can specify a triplet of delay values corresponding to rising transition, falling transition, and the delay to transition to 'z' (from '0' or '1' to 'z' --this is usually the delay for a three-state driver to turn off or float). We can do the same thing for net types,

wire #(0.5,0.6,0.7) a_z = a; // rise/fall/float delays

11.10.2   Pin-to-Pin Delay

The specify block [Verilog LRM 13] is a special construct in Verilog that allows the definition of pin-to-pin delays across a module. The use of a specify block can include the use of built-in system functions to check setup and hold times, for example. The following example illustrates how to specify pin-to-pin timing for a D flip-flop. We declare the timing parameters first followed by the paths. This example uses the UDP from Section 11.9.2, which does not include preset and clear (so only part of the flip-flop function is modeled), but includes the timing for preset and clear for illustration purposes.

module DFF_Spec; reg D, clk;
DFF_Part DFF1 (Q, clk, D, pre, clr);
initial begin D = 0; clk = 0; #1; clk = 1; end
initial ("T=%2g", ," clk=", clk," Q=", Q);
endmodule 
module DFF_Part(Q, clk, D, pre, clr);
  input clk, D, pre, clr; output Q; 
  DFlipFlop(Q, clk, D); // No preset or clear in this UDP.
  specify 
    specparam 
    tPLH_clk_Q = 3, tPHL_clk_Q = 2.9,
    tPLH_set_Q = 1.2, tPHL_set_Q = 1.1;
  (clk => Q) = (tPLH_clk_Q, tPHL_clk_Q);
  (pre, clr *> Q) = (tPLH_set_Q, tPHL_set_Q);
  endspecify
endmodule
T= 0 clk=0 Q=x
T= 1 clk=1 Q=x
T= 4 clk=1 Q=0

There are the following two ways to specify paths (module DFF_part above uses both) [Verilog LRM13.3]:

• x => y specifies a parallel connection (or parallel path) between x and y ( x and y must have the same number of bits).
• x *> y specifies a full connection (or full path) between x and y (every bit in x is connected to y) . In this case x and y may be different sizes.

The delay of some logic cells depends on the state of the inputs. This can be modeled using a state-dependent path delay. Here is an example:

`timescale 1 ns / 100 fs
module M_Spec; reg A1, A2, B; M M1 (Z, A1, A2, B);
initial begin A1=0;A2=1;B=1;#5;B=0;#5;A1=1;A2=0;B=1;#5;B=0; end
initial 
  ("T=%4g",," A1=",A1," A2=",A2," B=",B," Z=",Z);
endmodule 
`timescale 100 ps / 10 fs
module M(Z, A1, A2, B); input A1, A2, B; output Z; 
or (Z1, A1, A2); nand (Z, Z1, B); // OAI21
/*A1 A2 B Z  Delay=10*100 ps unless indicated in the table below.
  0  0  0 1 
  0  0  1 1
  0  1  0 1  B:0->1 Z:1->0 delay=t2
  0  1  1 0  B:1->0 Z:0->1 delay=t1
  1  0  0 1  B:0->1 Z:1->0 delay=t4
  1  0  1 0  B:1->0 Z:0->1 delay=t3
  1  1  0 1 
  1  1  1 0 */
specify specparam t1 = 11, t2 = 12; specparam t3 = 13, t4 = 14; 
  (A1 => Z) = 10; (A2 => Z) = 10;
  if (~A1) (B => Z) = (t1, t2); if (A1) (B => Z) = (t3, t4);
endspecify 
endmodule
T=   0 A1=0 A2=1 B=1 Z=x
T=   1 A1=0 A2=1 B=1 Z=0
T=   5 A1=0 A2=1 B=0 Z=0
T= 6.1 A1=0 A2=1 B=0 Z=1
T=  10 A1=1 A2=0 B=1 Z=1
T=  11 A1=1 A2=0 B=1 Z=0
T=  15 A1=1 A2=0 B=0 Z=0
T=16.3 A1=1 A2=0 B=0 Z=1

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