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11.4   Hierarchy

The module is the basic unit of code in the Verilog language [Verilog LRM 12.1],

module holiday_1(sat, sun, weekend);
  input sat, sun; output weekend;
  assign weekend = sat | sun;
endmodule

We do not have to explicitly declare the scalar wires: saturday , sunday , weekend because, since these wires appear in the module interface, they must be declared in an input , output , or inout statement and are thus implicitly declared. The module interface provides the means to interconnect two Verilog modules using ports [Verilog LRM 12.3]. Each port must be explicitly declared as one of input, output, or inout. Table 11.3 shows the characteristics of ports. Notice that a reg cannot be an input port or an inout port. This is to stop us trying to connect a reg to another reg that may hold a different value.

Within a module we may instantiate other modules, but we cannot declare other modules. Ports are linked using named association or positional association,

`timescale 100s/1s // Units are 100 seconds with precision of 1s.
module life; wire [3:0] n; integer days;
  wire wake_7am, wake_8am; // Wake at 7 on weekdays else at 8.
  assign n = 1 + (days % 7); // n is day of the week (1-7)
always@(wake_8am or wake_7am)
  ("Day=",n," hours=%0d ",(/36)%24,"  8am = ",
    wake_8am,"  7am = ",wake_7am,"  m2.weekday = ", m2.weekday);
  initial days = 0;
  initial begin #(24*36*10);; end // Run for 10 days.
  always #(24*36) days = days + 1; // Bump day every 24hrs.
  rest m1(n, wake_8am); // Module instantiation.
// Creates a copy of module rest with instance name m1,
// ports are linked using positional notation.
  work m2(.weekday(wake_7am), .day(n));
// Creates a copy of module work with instance name m2,
// Ports are linked using named association.
endmodule 
module rest(day, weekend); // Module definition.
// Notice the port names are different from the parent.
  input [3:0] day; output weekend; reg weekend;
  always begin #36 weekend = day > 5; end // Need a delay here.
endmodule 
module work(day, weekday);
  input [3:0] day; output weekday; reg weekday;
  always begin #36 weekday = day < 6; end // Need a delay here.
endmodule 
Day= 1 hours=0   8am = 0  7am = 0  m2.weekday = 0
Day= 1 hours=1   8am = 0  7am = 1  m2.weekday = 1
Day= 6 hours=1   8am = 1  7am = 0  m2.weekday = 0
Day= 1 hours=1   8am = 0  7am = 1  m2.weekday = 1

The port names in a module definition and the port names in the parent module may be different. We can associate (link or map) ports using the same order in the instantiating statement as we use in the module definition--such as instance m1 in module life . Alternatively we can associate the ports by naming them--such as instance m2 in module life (using a period '.' before the port name that we declared in the module definition). Identifiers in a module have local scope. If we want to refer to an identifier outside a module, we use a hierarchical name [Verilog LRM12.4] such as m1.weekend or m2.weekday (as in module life ), for example. The compiler will first search downward (or inward) then upward (outward) to resolve a hierarchical name [Verilog LRM 12.4-12.5].

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