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10.8  Type Declarations

In some programming languages you must declare objects to be integer, real, Boolean, and so on. VHDL (and ADA, the DoD programming language to which VHDL is related) goes further: You must declare the type of an object, and there are strict rules on mixing objects of different types. We say VHDL is strongly typed. For example, you can use one type for temperatures in Centigrade and a different type for Fahrenheit, even though both types are real numbers. If you try to add a temperature in Centigrade to a temperature in Fahrenheit, VHDL catches your error and tells you that you have a type mismatch.

This is the formal (expanded) BNF definition of a type declaration:

type_declaration ::= 
	type identifier ;
| type identifier is 
(identifier|'graphic_character' {, identifier|'graphic_character'}) ;
| range_constraint ;		| physical_type_definition ;
| record_type_definition ;	| access subtype_indication ;
| file of type_name ;		| file of subtype_name ;
| array index_constraint of element_subtype_indication ;
| array 
	(type_name|subtype_name range <>
		{, type_name|subtype_name range <>}) of
		element_subtype_indication ;

There are four type classes in VHDL [VHDL LRM3]: scalar types, composite types, access types, and file types. The scalar types are: integer type, floating-point type, physical type, and enumeration type. Integer and enumeration types are discrete types. Integer, floating-point, and physical types are numeric types. The range of an integer is implementation dependent but is guaranteed to include -2147483647 to +2147483647. Notice the integer range is symmetric and equal to -(2³¹- 1) to (2³¹- 1). Floating-point size is implementation dependent, but the range includes the bounds -1.0E38 and +1.0E38, and must include a minimum of six decimal digits of precision. Physical types correspond to time, voltage, current, and so on and have dimensions--a unit of measure (seconds, for example). Access types are pointers, useful in abstract data structures, but less so in ASIC design. File types are used for file I/O.

You may also declare a subset of an existing type, known as a subtype, in a subtype declaration. We shall discuss the different treatment of types and subtypes in expressions in Section 10.12.

Here are some examples of scalar type [VHDL LRM4.1] and subtype declarations [VHDL LRM4.2]:

entity Declaration_1 is end; architecture Behave of Declaration_1 is
type F is range 32 to 212; -- Integer type, ascending range.
type C is range 0 to 100; -- Range 0 to 100 is the range constraint.
subtype G is INTEGER range 9 to 0; -- Base type INTEGER, descending.
-- This is illegal: type Bad100 is INTEGER range 0 to 100; 
-- don't use INTEGER in declaration of type (but OK in subtype).
type Rainbow is (R, O, Y, G, B, I, V); -- An enumeration type.
-- Enumeration types always have an ascending range.
type MVL4 is ('X', '0', '1', 'Z'); 
-- Note that 'X' and 'x' are different character literals.
-- The default initial value is MVL4'LEFT = 'X'.
-- We say '0' and '1' (already enumeration literals
-- for predefined type BIT) are overloaded.
-- Illegal enumeration type: type Bad4 is ("X", "0", "1", "Z"); 
-- Enumeration literals must be character literals or identifiers.
begin end;

The most common composite type is the array type [VHDL LRM3.2.1]. The following examples illustrate the semantics of array declarations:

entity Arrays_1 is end; architecture Behave of Arrays_1 is
type Word is array (0 to 31) of BIT; -- a 32-bit array, ascending
type Byte is array (NATURAL range 7 downto 0) of BIT; -- descending
type BigBit is array (NATURAL range <>) of BIT;
-- We call <> a box, it means the range is undefined for now.
-- We call BigBit an unconstrained array.
-- This is OK, we constrain the range of an object that uses
-- type BigBit when we declare the object, like this:
subtype Nibble is BigBit(3 downto 0);
type T1 is array (POSITIVE range 1 to 32) of BIT;
-- T1, a constrained array declaration, is equivalent to a type T2 
-- with the following three declarations:
subtype index_subtype is POSITIVE range 1 to 32;
type array_type is array (index_subtype range <>) of BIT;
subtype T2 is array_type (index_subtype);
-- We refer to index_subtype and array_type as being
-- anonymous subtypes of T1 (since they don't really exist).
begin end;

You can assign values to an array using aggregate notation [VHDL LRM7.3.2]:

entity Aggregate_1 is end; architecture Behave of Aggregate_1 is
type D is array (0 to 3) of BIT; type Mask is array (1 to 2) of BIT;
signal MyData : D := ('0', others => '1'); -- positional aggregate 
signal MyMask : Mask := (2 => '0', 1 => '1'); -- named aggregate
begin end;

The other composite type is the record type that groups elements together:

entity Record_2 is end; architecture Behave of Record_2 is 
type Complex is record real : INTEGER; imag : INTEGER; end record;
signal s1 : Complex := (0, others => 1); signal s2: Complex;
begin s2 <= (imag => 2, real => 1); end;

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