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E> 9.2 Low-Level Design Languages

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9.2 Low-Level Design Languages

Schematics can be a very effective way to convey design information because pictures are such a powerful medium. There are two major problems with schematic entry, however. The first problem is that making changes to a schematic can be difficult. When you need to include an extra few gates in the middle of a schematic sheet, you may have to redraw the whole sheet. The second problem is that for many years there were no standards on how symbols should be drawn or how the schematic information should be stored in a netlist. These problems led to the development of design-entry tools based on text rather than graphics. As TTL gave way to PLDs, these text-based design tools became increasingly popular as de facto standards began to emerge for the format of the design files.

PLDs are closely related to FPGAs. The major advantage of PLD tools is their low cost, their ease of use, and the tremendous amount of knowledge and number of designs, application notes, textbooks, and examples that have been built up over years of their use. It is natural then that designers would want to use PLD development systems and languages to design FPGAs and other ASICs. For example, there is a tremendous amount of PLD design expertise and working designs that can be reused.

In the case of ASIC design it is important to use the right tool for the job. This may mean that you need to convert from a low-level design medium you have used for PLD design to one more appropriate for ASIC design. Often this is because you are merging several PLDs into a single, much larger, ASIC. The reason for covering the PLD design languages here is not to try and teach you how to use them, but to allow you to read and understand a PLD language and, if necessary, convert it to a form that you can use in another ASIC design system.

9.2.1 ABEL

ABEL is a PLD programming language from Data I/O. Table 9.2 shows some examples of the ABEL statements. The following example code describes a 4:1 MUX (equivalent to the LS153 TTL part):

TABLE 9.2 ABEL.
Statement	Example	Comment
Module	module MyModule	You can have multiple modules.
Title	title 'Title in a String'	A string is a character series between quotes.
Device	MYDEV device '22V10' ;	MYDEV is Device ID for documentation. 22V10 is checked by the compiler.
Comment	"comments go between double quotes" "end of line is end of comment	The end of a line signifies the end of a comment; there is no need for an end quote.
@ALTERNATE	@ALTERNATE "use alternate symbols	operator	alternate	default
		AND OR NOT XOR XNOR	* + / :+: :*:	& # ! $ !$
Pin declaration	MYINPUT pin 2; I3, I4 pin 3, 4 ; /MYOUTPUT pin 22; IO3,IO4 pin 21,20 ;	Pin 22 is the IO for input on pin 2 for a 22V10. MYOUTPUT is active-low at the chip pin. Signal names must start with a letter.
Equations	equations	Defines combinational logic.
	IO4 = HELPER ; HELPER = /I4 ;	Two-pass logic
Assignments	MYOUTPUT = /MYINPUT ;	Equals '=' is unlocked assignment.
	IO3 := I4 ;	Clocked assignment operator (registered IO)
Signal sets	D = [D0, D1, D2, D3] ; Q = [Q0, Q1, Q2, Q3];	A signal set, an ABEL bus
	Q := D ;	4-bit-wide register
Suffix	MYOUTPUT.RE = CLR ;	Register reset
	MYOUTPUT.PR = PRE ;	Register preset
Addition	COUNT = [D0, D1, D2]; COUNT := COUNT + 1;	Can’t use @ALTERNATE if you use '+' to add.
Enable	ENABLE IO3 = IO2; IO3 = MYINPUT;	Three-state enable (ENABLE is a keyword). IO3 must be a three-state pin.
Constants	K = [1, 0, 1] ;	K is 5.
Relational	IO# = D == K5 ;	Operators: == != < > <= >=
End	end MyModule	Last statement in module

module MUX4

title '4:1 MUX'

MyDevice device 'P16L8' ;

@ALTERNATE

"inputs

A, B, /P1G1, /P1G2 pin 17,18,1,6 "LS153 pins 14,2,1,15

P1C0, P1C1, P1C2, P1C3 pin 2,3,4,5 "LS153 pins 6,5,4,3

P2C0, P2C1, P2C2, P2C3 pin 7,8,9,11 "LS153 pins 10,11,12,13

"outputs

P1Y, P2Y pin 19, 12 "LS153 pins 7,9

equations

P1Y = P1G*(/B*/A*P1C0 + /B*A*P1C1 + B*/A*P1C2 + B*A*P1C3);

end MUX4

9.2.2 CUPL

CUPL is a PLD design language from Logical Devices. We shall review the CUPL 4.0 language here. The following code is a simple CUPL example describing sequential logic:

SEQUENCE BayBridgeTollPlaza {

PRESENT red

IF car NEXT green OUT go; /* conditional synchronous output */

DEFAULT NEXT red; /* default next state */

PRESENT green

NEXT red; } /* unconditional next state */

This code describes a state machine with two states. Table 9.3 shows the different state machine assignment statements.

TABLE 9.3 CUPL statements for state-machine entry.
Statement			Description
IF	NEXT		Conditional next state transition
IF	NEXT	OUT	Conditional next state transition with synchronous output
	NEXT		Unconditional next state transition
	NEXT	OUT	Unconditional next state transition with asynchronous output
		OUT	Unconditional asynchronous output
IF		OUT	Conditional asynchronous output
DEFAULT	NEXT		Default next state transition
DEFAULT		OUT	Default asynchronous output
DEFAULT	NEXT	OUT	Default next state transition with synchronous output

You may also encode state machines as truth tables in CUPL. Here is another simple example:

FIELD input = [in1..0];

FIELD output = [out3..0];

TABLE input => output {00 => 01; 01 => 02; 10 => 04; 11 => 08; }

The advantage of the CUPL language, and text-based PLD languages in general, is now apparent. First, we do not have to enter the detailed logic for the state decoding ourselves—the software does it for us. Second, to make changes only requires simple text editing—fast and convenient.

Table 9.4 shows some examples of CUPL statements. In CUPL Boolean equations may use variables that contain a suffix, or an extension , as in the following example:

output.ext = (Boolean expression);

TABLE 9.4 CUPL.
Statement	Example	Comment
Boolean expression	A = !B;	Logical negation
	A = B & C;	Logical AND
	A = B # C;	Logical OR
	A = B $ C;	Logical exclusive-OR
Comment	A = B & C /* comment */
Pin declaration	PIN 1 = CLK;	Device dependent
	PIN = CLK;	Device independent
Node declaration	NODE A;	Number automatically assigned
	NODE [B0..7];	Array of buried nodes
Pinnode declaration	PINNODE 99 = A;	Node assigned by designer
	PINNODE [10..17] = [B0..7];	Array of pinnodes
Bit-field declaration	FIELD Address = [B0..7];	8-bit address field
Bit-field operations	add_one = Address:FF;	True if Address = OxFF
	add_zero = !(Address:&);	True if Address = Ox00
	add_range = Address:[0F..FF];	True if 0F.LE.Address.LE.FF

The extensions steer the software, known as a fitter , in assigning the logic. For example, a signal-name suffix of .OE marks that signal as an output enable.

Here is an example of a CUPL file for a 4-bit counter placed in an ATMEL PLD part that illustrates the use of some common extensions:

Name 4BIT; Device V2500B;

/* inputs */

pin 1 = CLK; pin 3 = LD_; pin 17 = RST_;

pin [18,19,20,21] = [I0,I1,I2,I3];

/* outputs */

pin [4,5,6,7] = [Q0,Q1,Q2,Q3];

field CNT = [Q3,Q2,Q1,Q0];

/* equations */

Q3.T = (!Q2 & !Q1 & !Q0) & LD_ & RST_ /* count down */

# Q3 & !RST_ /* ReSeT */

# (Q3 $ I3) & !LD_; /* LoaD*/

Q2.T = (!Q1 & !Q0) & LD_ & RST_ # Q2 & !RST_ # (Q2 $ I2) & !LD_;

Q1.T = !Q0 & LD_ & RST_ # Q1 & !RST_ # (Q1 $ I1) & !LD_;

Q0.T = LD_ & RST_ # Q0 & !RST_ # (Q0 $ I0) & !LD_;

CNT.CK = CLK; CNT.OE = 'h'F; CNT.AR = 'h'0; CNT.SP = 'h'0;

In this example the suffix extensions have the following effects: .CK marks the clock; .T configures sequential logic as T flip-flops; .OE (wired high) is the output enable; .AR (wired low) is the asynchronous reset; and .SP (wired low) is the synchronous preset. Table 9.5 shows the different CUPL extensions.

TABLE 9.5 CUPL 4.0 extensions.
Extension 1		Explanation	Extension		Explanation
D	L	D input to a D register	DFB	R	D register feedback of combinational output
L	L	L input to a latch	LFB	R	Latched feedback of combinational output
J, K	L	J-K-input to a J-K register	TFB	R	T register feedback of combinational output
S, R	L	S-R input to an S-R register	INT	R	Internal feedback
T	L	T input to a T register	IO	R	Pin feedback of registered output
DQ	R	D output of an input D register	IOD/T	R	D/T register on pin feedback path selection
LQ	R	Q output of an input latch	IOL	R	Latch on pin feedback path selection
AP, AR	L	Asynchronous preset/reset	IOAP, IOAR	L	Asynchronous preset/reset of register on feedback path
SP, SR	L	Synchronous preset/reset	IOSP, IOSR	L	Synchronous preset/reset of register on feedback path
CK	L	Product clock term (async.)	IOCK	L	Clock for pin feedback register
OE	L	Product-term output enable	APMUX, ARMUX	L	Asynchronous preset/reset multiplexor selection
CA	L	Complement array	CKMUX	L	Clock multiplexor selector
PR	L	Programmable preload	LEMUX	L	Latch enable multiplexor selector
CE	L	CE input of a D-CE register	OEMUX	L	Output enable multiplexor selector
LE	L	Product-term latch enable	IMUX	L	Input multiplexor selector of two pins
OBS	L	Programmable observability of buried nodes	TEC	L	Technology-dependent fuse selection
BYP	L	Programmable register bypass	T1	L	T1 input of 2-T register

The 4-bit counter is a very simple example of the use of the Atmel ATV2500B. This PLD is quite complex and has many extra “buried” features. In order to use these features in CUPL (and ABEL) you need to refer to special pin numbers and node numbers that are given in tables in the manufacturer’s data sheets. You may need the pin-number tables to reverse engineer or convert a complicated CUPL (or ABEL) design from one format to another.

Atmel also gives skeleton headers and pin declarations for their parts in their data sheets. Table 9.6 shows the headers and pin declarations in ABEL and CUPL format for the ATMEL ATV2500B.

TABLE 9.6 ABEL and CUPL pin declarations for an ATMEL ATV2500B.

ABEL

CUPL

device_id device 'P2500B';

"device_id used for JEDEC filename

I1,I2,I3,I17,I18 pin 1,2,3,17,18;

O4,O5 pin 4,5 istype 'reg_d,buffer';

O6,O7 pin 6,7 istype 'com';

O4Q2,O7Q2 node 41,44 istype 'reg_d';

O6F2 node 43 istype 'com';

O7Q1 node 220 istype 'reg_d';

device V2500B;

pin [1,2,3,17,18] = [I1,I2,I3,I17,I18];

pin [7,6,5,4] = [O7,O6,O5,O4];

pinnode [41,65,44] = [O4Q2,O4Q1,O7Q2];

pinnode [43,68] = [O6Q2,O7Q1];

9.2.3 PALASM

PALASM is a PLD design language from AMD/MMI. Table 9.7 shows the format of PALASM statements. The following simple example (a video shift register) shows the most basic features of the PALASM 2 language:

TABLE 9.7 PALASM 2.
Statement	Example	Comment
Chip	CHIP abc 22V10	Specific PAL type
	CHIP xyz USER	Free-form equation entry
Pinlist	CLK /LD D0 D1 D2 D3 D4 GND NC Q4 Q3 Q2 Q1 Q0 /RST VCC	Part of CHIP statement; PAL pins in numerical order starting with pin 1
String	STRING string_name 'text'	Before EQUATIONS statement
Equations	EQUATIONS	After CHIP statement
	A = /B	Logical negation
	A = B * C	Logical AND
	A = B + C	Logical OR
	A = B :+: C	Logical exclusive-OR
	A = B :*: C	Logical exclusive-NOR
Polarity inversion	/A = /(B + C)	Same as A = B + C
Assignment	A = B + C	Combinational assignment
	A := B + C	Registered assignment
Comment	A = B + C ; comment	Comment
Functional equation	name.TRST	Output enable control
	name.CLKF	Register clock control
	name.RSTF	Register reset control
	name.SETF	Register set control

TITLE video ; shift register

CHIP video PAL20X8

CK /LD D0 D1 D2 D3 D4 D5 D6 D7 CURS GND NC REV Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 /RST VCC

STRING Load 'LD*/REV*/CURS*RST' ; load data

STRING LoadInv 'LD*REV*/CURS*RST' ; load inverted of data

STRING Shift '/LD*/CURS*/RST' ; shift data from MSB to LSB

EQUATIONS

/Q0 := /D0*Load+D0*LoadInv:+:/Q1*Shift+RST

/Q1 := /D1*Load+D1*LoadInv:+:/Q2*Shift+RST

/Q2 := /D2*Load+D2*LoadInv:+:/Q3*Shift+RST

/Q3 := /D3*Load+D3*LoadInv:+:/Q4*Shift+RST

/Q4 := /D4*Load+D4*LoadInv:+:/Q5*Shift+RST

/Q5 := /D5*Load+D5*LoadInv:+:/Q6*Shift+RST

/Q6 := /D6*Load+D6*LoadInv:+:/Q7*Shift+RST

/Q7 := /D7*Load+D7*LoadInv:+:Shift+RST;

The order of the pin numbers in the previous example is important; the order must correspond to the order of pins for the DEVICE . This means that you probably need the device data sheet in order to be able to translate a design from PALASM to another format by hand. The alternative is to use utilities that many PLD and FPGA companies offer that automatically translate from PALASM to their own formats.

1. L means that the extension is used only on the LHS of an equation; R means that the extension is used only on the RHS of an equation.

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9.2 Low-Level Design Languages

9.2.1 ABEL

9.2.2 CUPL

9.2.3 PALASM

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